
// DFF
module dff
#(
	parameter DW = 1
)(
	input 		    	 clk,
	input 		    	 en,
	input [DW-1:0]  	 d,
	output logic[DW-1:0] q
);

always @(posedge clk) begin
	if(en)
		q <= d;
end

endmodule

module dffr
#(
	parameter DW = 1,
	parameter DV = 0
)(
	input 		    	 clk,
	input 				 rst_n,
	input 		    	 en,
	input [DW-1:0]  	 d,
	output logic[DW-1:0] q
);

always @(posedge clk or negedge rst_n) begin
	if(~rst_n)
		q <= DV;
	else if(en)
		q <= d;
end
	
endmodule
